Reference.

Goals, constraints, architecture decisions, timeline.

Verified SA BOM with supplier URLs and variants.

Hardware block diagram, pin map, I²C, power rules.

Repo forks, library deps, module layout, tasks T1–T17.

STL selection, print settings, link-length calibration.

IK math, tripod/ripple/wave gait specs.

Per-servo trim and direction-flipping.

Five phases with acceptance criteria per phase.

Every URL used in the brief, grouped by purpose.

LiPo + power pre-flight (source for §04).

Mistakes in earlier briefs to avoid replicating.